The Static Random Access Memory is widely used among digital circuits for its good trade-off between memory architectures. Being not large like register files, at the same time not slow as DRAM or hard disk management. It is also compatible with standard CMOS process.
The standard SRAM cell architecture is shown above, a pair of pMOS and nMOS transistors create cross-coupled inverters that can hold its state without needing to have its input driven by an extern signal.
The word line “WL” enables the bit lines “BL and “!BL” to drive the net “Q” to a logical value (either 0 or 1) and at the same time, opening the cell data to be read by a special circuitry.
Sizing those transistors correctly is required. If the inverter transistors “M1 to M4” are considerably stronger than “M5” and “M6” access transistors, the current passing through the transistors “M5 and M6” will not be enough to flip the state of the memory cell. The stable state created by the cross-coupled inverters needs to be overpowered to change its logical level. Moreover, the opposite situation with unbalanced strength (size) causes the logical state to be changed from bit lines noise even with the word lines disabled. The same problem can happen during the read operation which is going to be presented further.
The circuit structure is built on Cadence Virtuoso Schematic Editor, to show the write operation on a standard SRAM cell. The schematic contains two power sources for Vdd and GND and two pulse generators to drive the word line and bitlines.
The plot acquired above is based upon a well sized SRAM cell, when the “WORD” trace is high, enables the “BIT” from bit lines to drive the “DATA” of the cell. The book “CMOS VLSI Design: A circuit and Systems Perspective” tells that a good sizing can be achieved with the pull-down transistors 8/2 λ, pull-up 3/3 λ and access transistors with 4/2 λ.
With oversized pull-up and pull-down transistors, the access transistors will not have enough power to flip the logical cell level as shown above.
An array of SRAM cells is constructed by sharing the word line for multiple cells. Multiple arrays may have different words that become the programming address. The output of a decoder chooses specific rows or columns. A matrix can also be built with a similar cell schematic and two decoders controlling row and column to select a particular cell. As the memory size gets bigger, more capacitance (intrinsic from transistors) is connected to the shared cells bit lines. This capacitance brings the need of special circuitry to read the data of the cell. The access transistors are not designed to quickly drive the bit lines to a determined value and increasing the cells would reduce the memory size capability.
As the memory size gets bigger, more capacitance (intrinsic from transistors) is connected to the shared cells bit lines. This capacitance brings the need of special circuitry to read the data of the cell. The access transistors are not designed to quickly drive the bit lines to a determined value and increasing the cells would reduce the memory size capability.
(Circuit took from the book “CMOS Circuit Design, Layout, and Simulation”)
The sense amplifier circuit (above) is used to measure which bit line is higher and then amplify it. Both bit lines (“BL” and “!BL”) must be set to a logical ‘1’ before the sensing begins. The same logical level is necessary since the SRAM access transistors slowly drive the bit lines when a SRAM cell is selected to be read. Similar to a SRAM cell, the schematic consists of a pair of weak cross-coupled inverters, access transistors, and another transistor to control the “floating” state.
A test bench is set to observe the output signals of the sense amplifier. A pulse source is used to control the “SE” (Sense Enable) signal. Two ramp functions are generated from a PWL source to simulate the slowly bit line transition provoked by a selected SRAM cell.
At the transient simulation presented above, when the “SE” signal is set to a logical ‘0’ (pMOS control), the bottom nMOS transistor cuts the cross-coupled inverters connection to “GND” global net, making them to be in a floating state. At the same time, the access transistors are enabled, letting “Q and !Q” nets to be charged by the bit lines. Sequentially, raising “SE” to a logical ‘1’ disables the cross-coupled inverters connection to the bitlines and let the cell to be in a stable state with “GND”. A race condition happens which makes the “most charged” node to overpower the other one, showing a solid logic state at its outputs.