The following project was developed during a class taken at Federal University of Rio Grande do Norte with professor Marcelo. The group was composed by Giovanna, João, Raí and me.
The group goal was to implement a drying grain system. The process of drying should start with the press of a button, after that, a fan speed is controlled based on a “dry curve” and the reading of a luminosity and temperature sensor. With 3 minutes the routine is finished, and the machine should wait for another button press to start the system again.
The hardware of the control system consists of:
- An ATmega2560 Microcontroller
- An LDR to sense the luminosity
- An NTC sensor for the temperature
- A Push-Button to start the system
- LEDs for behavior visualization
- A “4N25” Photocoupler to protect the Microcontroller from the load
- An NPN transistor with a diode for circuit protection
- Power supply to the Fan
- Some resistors
The last picture represents the components, an Arduino Mega board is used to facilitate communication with the microprocessor, the DC motor illustrates the fan. Since the LDR and NTC sensors are a variable resistance for the desired domain, a voltage divider is applied to convert the input voltage to a measured voltage. An operational range should be specified in this type of configuration, in the example of the NTC temperature sensor, the fixed resistor was chosen based on its measured resistance at the ambient temperature which, for 25 °C is approximately 50Ω.
This post is an extension of “Creating a simple overlay for PYNQ-Z1 board from Vivado HLx“, which presented an Overlay creation methodology for an accelerator block. The implemented block only communicates with Zynq Processing System (PS) and does not explain the PYNQ peripherals management. This work was developed with the help of Wagner Wesner.
The “base” Overlay found inside the PYNQ package is composed of the basic structures needed to handle PYNQ functionalities. The Vivado project (built on Vivado 2016.1) used to develop the “base” Overlay can be reconstructed from the Tcl file and observed:
The content presented in this post was developed during the winter class given at Federal University of Rio Grande do Norte, with professors Carlos Valderrama and Samuel Xavier. My group was composed by Wagner Wesner and me.
Our group task was targeting Vivado HLS to implement accelerator blocks for the PYNQ-Z1 board. The PYNQ consists of a board with some peripherals and a ZYNQ chip, the ZYNQ has a cluster with a Central Processing Unit (CPU) and a Field-Programmable Gate Array (FPGA) which enables the test of the synthesized blocks on Vivado. Vivado outputs such as a bitstream and a Tcl file are used to create a PYNQ overlay. The overlay is further used to communicate the generated blocks with the PYNQ python interface.
The High-Level Synthesis (HLS) is very useful to transform complex algorithms into Hardware Description Language (HDL) code. There is a variety of algorithms which takes considerable CPU processing time, those algorithms can be translated to a hardware description which can be implemented on an FPGA. Once the circuit is configured on the FPGA, the algorithm time demanding tasks are parallelized (summing up), which increases performance and brings other potential benefits.
The Vivavo HLS software starts the PYNQ overlay creation with a custom block.