The intention of this post is to show all the steps required to successfully fabricate a chip with Cadence environment using NCSU 0.5um standard digital library. It is important to highlight that this tutorial will show a lot of details that can be adapted to other CAD tools or technologies, it can also be used to implement mixed-signal projects by including the digital layout inside Virtuoso. I find it helpful since it is difficult to find such content on the internet. Likewise, I am not going to go deep on the tools capabilities, but explore the basic steps to have a final product. With the exception of the Cadence tools, you can get a totally free chip using the NCSU design kit and the MOSIS service (if you are attached to a university). The process steps may differ depending on the system is being used.
The beginning of the digital flow starts with a Verilog/VHDL code specified by the desired project. For the sake of simplicity, let’s use a Verilog code which implements a 8-bit counter:
module up_counter( out, enable, clk, reset ); output [7:0] out; input enable, clk, reset; reg [7:0] out; always @(posedge clk) if (reset) begin out <= 8'b0 ; end else if (enable) begin out <= out + 1; end endmodule
And its testbench:
`include "up_counter.v" module up_counter_tb; wire [7:0] out; reg enable, clk, reset; up_counter U0( .out (out), .enable (enable), .clk (clk), .reset (reset) ); initial begin $monitor("out=%8b enable=%b clk=%b reset=%b", out,enable,clk,reset); enable=1; reset=0; clk=0; #1 reset=1; #1 clk=1; #1 reset=0; clk=0; #1 repeat(300) #20 clk = ~clk; end endmodule
The simulation can be performed with the NCSim tool “irun”, running on a graphical window or the terminal. To run on a graphical window (SimVision):
irun -gui -access rwc up_counter_tb.v
After the window pops-up, click on the instance “up_counter_tb” and after “Send To: Waveform”. Press “Run” and the simulation results can be seen: