The utilization of a Vector File makes controlling multiple input and output signals independently possible. Its implementation is important for a variety of circuits which need different pulses at specific times, relieving the effort to manage PWL voltage sources at schematic.
Note: comments begins with “;” character
radix 1 1 4 4 ; radix specifies the number of ports and number of bits for each port, ; the base number is also specified ( from binary '1' to hexadecimal '4' ) io i i i i ; io defines the state of each port, as input "i", output "o" ; or bidirectional "b" vname Primeiro_Sinal Segundo_Sinal Terceiro_Sinal[0:3] Quarto_Sinal,Quinto_Sinal,Sexto_Sinal,Setimo_Sinal ; vname sets the name of each port tunit 1ns ; tunit configures the time unit of simulation trise 1ps ; trise defines the rise time of each vector tfall 1ps ; tfall defines fall time of each vector vih 5.0 ; vih defines logical '1' voltage vil 0.0 ; vil defines logical '0' voltage period 10.0 ; period determines the time interval between each vector step, the ; number is multiplied by the previously time unit set idelay 5 0 1 1 0 ; idelay inserts a delay at the selected ports multiplied by the time unit ; The next lines will define the states of each port as the ; transient simulation happens, each line represents a time step ; The binary number can be represented with 0 or 1, and the ; hexadecimals with 0-F 0 0 0 0 ; All signals initially set to 0 1 0 F F ; First signal with a logical '1', second with a logical '0' , the other ones set to a logical '1' 0 1 C C ; And goes on 1 0 A A 1 1 3 3
The ports declaration and manipulation are indented by its position from left to right.