The Static Random Access Memory is widely used among digital circuits for its good trade-off between memory architectures. Being not large like register files, at the same time not slow as DRAM or hard disk management. It is also compatible with standard CMOS process.
The standard SRAM cell architecture is shown above, a pair of pMOS and nMOS transistors create cross-coupled inverters that can hold its state without needing to have its input driven by an extern signal.
The word line “WL” enables the bit lines “BL and “!BL” to drive the net “Q” to a logical value (either 0 or 1) and at the same time, opening the cell data to be read by a special circuitry.
Sizing those transistors correctly is required. If the inverter transistors “M1 to M4” are considerably stronger than “M5” and “M6” access transistors, the current passing through the transistors “M5 and M6” will not be enough to flip the state of the memory cell. The stable state created by the cross-coupled inverters needs to be overpowered to change its logical level. Moreover, the opposite situation with unbalanced strength (size) causes the logical state to be changed from bit lines noise even with the word lines disabled. The same problem can happen during the read operation which is going to be presented further.